Engineering and Information Technology Collected Works - Theses
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ItemA distributed logic computer(University of Melbourne, 1978)This thesis describes the development of a distributed logic computer. The computer employs a large number of processing cells instead of the usual single central processor connected to a large number of memory "cells". Each processing cell can contain either data or a stored instruction. In addition each processing cell is able to execute an instruction communicated to it. Instructions are transmitted from the cell in which they are stored to the data cell on which they are to act. At the completion of execution of an instruction/ the data cell concerned itself transmits an instruction to the next stored instruction to be transmitted for execution. The address of the following instruction cell is contained in the instruction previously executed, that is each transmitted instruction also contains the address of its successor, unless execution of the instruction stream is to cease. Communication between processing cells is accomplished by means of a communication network. This network consists of a tree-like arrangement of interconnected communication cells which conveys messages (instructions) from a source processing cell to a destination processing cell. The network employs packet switching using a relative processing cell address. Since no central processor is employed, there is no centralised control of address selection or execution. An arbitrary number of execution streams may proceed concurrently. Instructions have been provided which allow program divergence, to achieve parallelism, and which provide synchronisation at the completion of concurrent processes. A scheduling queue is included at the root of the communication network to provide mutual exclusion for critical resources. The problem of deadlock and the solutions used are discussed in some detail. The development and design features of the computer are described and the performance of both the communication network itself, and the processor as a whole, is discussed. The processor has been simulated in detail to allow a quantitative evaluation of various aspects of performance. The unique programming techniques associated with the processor are illustrated in detail. A symbolic cross-assembler has been used in conjunction with the simulator to assist in program preparation for execution, and assembly listings are included in illustrating programming techniques. One technique in particular which has received attention is referred to as "software pipelining" and measurements of performance of representative programs are discussed. Data flow principles are also examined in relation to the principles of operation of this computer.