Electrical and Electronic Engineering - Theses
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ItemA highly flexible stimulator for a high acuity retinal prosthesis implemented in 65 nm CMOS process( 2011)This thesis presents a design of a flexible stimulator in 65 nm Complementary Metal Oxide Semiconductor (CMOS) as part of a 1024-electrode epiretinal prosthesis to restore partial vision in patients suffering from eye diseases such as retinitis pigmentosa (RP) and age-related macular degradation (AMD). The stimulator design is to support as many different stimulation strategies as possible. In particular, a wide variety of current amplitudes and stimulation frequencies is called for. Bipolar as well as monopolar stimulation strategies are also catered for. The selection of electrodes is fully flexible where any electrodes and any number of them can be selected as active or return at any time slice. The separation of image data update rate and stimulation refresh rate helps reduce data bandwidth by a half, which is very beneficial because the bandwidth for the data receiver of the stimulator chip is limited to 300 kHz in Medical Implant Communication Service (MICS) band. A distributed design where data is mainly processed at the local controller of every electrode driver simplifies signal routing, which is critical when the number of electrodes goes up to 1024. Global controlling circuits which help realizing some of the flexibility were designed, fabricated and tested with good performance. A novel electrode driver topology was proposed. Each electrode is controlled by its own driver, which helps selecting electrodes independently. The proposed electrode driver allows its electrode to act as active or return. The novel electrode driver operates in an alternately push-pull manner where only one current sink or source works at a time when doing stimulation. This results in a reduction of headroom voltage by a half, or equivalently more voltage can be used for stimulation, which is extremely advantageous as the maximum supply voltage of the implemented 65 nm CMOS process is limited to 3.3V. In order to verify the feasibility of the flexibility in terms of the ability of circuit implementation and power consumption, a prototype stimulator with 64 outputs was designed, fabricated, and tested. This prototype stimulator supports all the targeted stimulation flexibility. The verification of this prototype stimulator is a very useful and important preparation stage in designing a fully integrated high acuity epiretinal stimulator. The prototype stimulator was extensively tested and expected performance has been achieved. The power consumption of the prototype stimulator is 400 µW excluding the stimulus power, which makes the power consumption of the ultimate 1024-electrode stimulator just a few mW.
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ItemA super low power MICS band receiver on 65 nm CMOS for high resolution retinal prosthesis( 2011)Implantable biomedical communication devices are now at the forefront of extensive research. These devices may effectively capture vital information from the outside environment for patients to use as substitutes of human organs (e.g. bionic ear, bionic eye, etc.), and/or record real-time physiological parameters from a patient (e.g. electrocardiogram, electroencephalogram, electromyogram, blood pressure, etc.). Transceivers for these purposes require extremely low power consumption, since batteries are undesirable due to their limited lifetime and the possibility of infections, and hence power is preferably acquired by wireless coupling. Moreover, these transceivers are usually preferred to be fully integrated on a single chip for easier surgery and better biocompability. Medical Implant Communication Service (MICS) band (402 MHz - 405 MHz with 10 channels), which was established by the Federal Communications Commission (FCC) of the United States in 1999, is widely used as the operation frequency band for biomedical devices. This thesis presents a super low power MICS band receiver for a fully integrated retinal prosthesis (Bionic Eye). In order to achieve super low total power consumption, all the analog blocks in this work are operated in subthreshold region and various low power techniques are applied. The fully subthreshold operation in MICS band is become possible due to the use of sub-70 nm Complementary Metal Oxide Semiconductor (CMOS) technology. This thesis starts with the power considerations in deep sub-micron CMOS and analyses the limits and challenges in low power radio frequency (RF) and analog design. It then considers subthreshold operation and provides parameter extraction approaches for the Enz-Krummenacher-Vittoz (EKV) model, as well as the modeling of transconductance efficiencies for various types of field-effect transistor (FET) devices. A literature review of MICS receivers is also included, in order to gain an intuitive insight into the current state of the art and the basic approaches that can be used for low power design. After presenting the system architecture and system level calculations, the individual block designs are reported one by one. The first block is the front-end down converter. This down converter, including a low-noise amplifier (LNA) and a quadrature mixer, only draws 500-μA bias current under 1-V supply. With a small differential local oscillation (LO) swing of 300 mV, it provides a voltage conversion gain of 34 dB and a noise figure of 7 dB, while a -27.5-dBm input-referred third-order intercept point (IIP3) is obtained. A power-constrained noise optimization technique is applied to this subthreshold down converter to optimize the matching parameters and transistor sizes. The second block is the channel selection filter. A 5th-order elliptic operational transconductance amplifier-capacitor (OTA-C) bandpass filter utilizes subthreshold inverter-based OTAs is designed. In order to broaden input range of the filter, the first OTA stage is linearized by using the active-error feedforward technique. The overall filter only draws 320-μA bias current under 1-V supply, while having an input range up to 0.6 Vpp and an in-band spurious free dynamic range (SFDR) of 41 dB. By using N-type FET capacitors as OTAs’ load, the chip area of this filter is minimized. Apart from the real bandpass filter, a 7th-order complex filter that has 48-dB image rejection at cost of 500-μW power dissipation is also constructed for the occasions that there exist image frequency interferences. As MICS band channel selection filters, both the real and complex filters have approximately 300-kHz bandwidths and exhibit more than 40-dB attenuations to the adjacent channel. The third block is the intermediate frequency (IF) variable gain amplifier (VGA). This VGA consists of a variable gain stage, followed by a fixed gain stage. It has a 32 dB log-linear tuning range and only requires 46-μA bias current under 1-V supply. The above three blocks constitute the receiver chain, which has a tunable total voltage gain of 36.8-68.9 dB on 50-Ω load and a noise figure of 17.2-15.1 dB. The measured gain and noise figure at designed normal operation condition, for a RF input power of -70 dBm, are 57.3 dB and 15.7 dB respectively. This thesis also reports on a subthreshold voltage-controlled oscillator (VCO) and a low power phase-locked loop (PLL), which are designed to provide LO signals for both receiver and transmitter in multi-channel operation. Current-reuse topology that uses N-type and P-type CMOS cross-coupled pairs is chosen for the core VCO design to save power. Cascade on-chip inductors are used and a pair of ”nCap” varactors (N-type FET in N-well) is configured to give a VCO gain of 12 MHz/V. The VCO is able to produce 600-mVpp quadrature signal whilst only dissipating 220 μW. The PLL utilizes digital frequency synthesizer and can settle within 350 μS while possessing a low phase noise, less than -102 dBc/Hz at 200-kHz offset. The average power dissipation of the entire PLL is a mere 400 μW. A 300-MHz microelectromechanical (MEMS) resonator is proposed to generate the system’s frequency reference. After comparing different types of MEMS devices and their post-CMOS micro-machining processes, a contour mode nickel disk resonator is selected. The precise modeling and simulations ensure it has a quality factor as high as 9000. The integration of the receiver chain with the PLL, including electrostatic discharge (ESD) protections, are demonstrated on a test chip using IBM 10cmoslpe 65-nm process. The performances of all individual blocks are measured and documented. Finally, experimental results of the entire receiver are reported and block power consumptions are experimentally established. The extremely low power dissipation and MICS band operation ensure that this receiver is very suitable for biomedical applications such as the Bionic Eye.