Electrical and Electronic Engineering - Theses
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ItemDesign and signal processing for CMOS automotive radar( 2014)There is an increasing use of radar for sensing the environment in automotive applications to provide data for applications such as collision avoidance and adaptive cruise control systems. In this thesis, the waveform design, signal processing and architecture of automotive radars are explored. A particular emphasis is placed on reducing the implementation cost to enable widespread adoption of safety systems. While an automotive radar is unlikely to experience intentional jamming, the anticipated increase in density of radars with falling cost and improved availability is expected to lead to more interference as more users begin to share the available band. It is thus important that the performance of the system is understood in the presence of interference. This thesis provides some insight into the severity of the problem and some strategies for mitigating the impact. The requirements of automotive radar typically mandate the use of full-amplitude continuous-wave radar transmitters which occupy as much bandwidth as possible to meet the constraints on transmitted power for detecting targets at long range. Thus, some of the usual interference mitigation techniques in mobile communications such as power control or frequency or time division are not readily applicable. Instead, the available spectrum must be shared with a code-division multiple access scheme. It is important to have an understanding of the availability of safety applications under interference. Thus, a simple but typical automotive interference environment is modelled under the assumption that a multiple access scheme is employed. The model is used to determine empirical guides on the number of effective channels required under various scenarios, as well as to understand the average and worst case times that users will be blocked. Two classes of frequency modulated waveforms are investigated in this thesis. First, Linear Frequency Modulated Continuous Wave (LFM-CW), which has emerged as a popular choice in automotive radar because it readily admits a simple transceiver architecture. The return signals are usually processed using FFTs. However, mitigating interference with such waveforms requires the sacrifice of some estimation performance. A second scheme of using Random Stepped Frequency (RSF) waveforms scheduled in conjunction with single tone continuous wave (CW) waveforms is also presented. A common transceiver architecture can be used but the estimation performance of the RSF waveform can be improved with more sophisticated signal processing beyond the typical limits imposed by the FFT processing typically used with LFM-CW waveforms, while still maintaining low sampling and data rates. The performance of the algorithm when the system is in a non-optimal state due to interference or hardware limitations is demonstrated to degrade gracefully. The waveform also lends itself to interference mitigation as in each time slot each user is only concerned with a small part of the full band. The increased flexibility of RSF waveforms will thus allow radars to operate cognitively by rearranging their transmitted sequence when spurious returns from other users are detected.
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ItemDesign and implementation of an 11-bit 50-MS/s ADC on 65-nm CMOS process( 2013)This thesis presents the design and implementation of an 11-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). This ADC features a comparator with input-referred offset cancellation, an improved split capacitor digital-to-analog converter (CDAC), and CDAC linearity calibration. In the design of the high-speed high-resolution comparator, kickback noise is suppressed by an intermediate stage. A switch is inserted between the regeneration nodes in order to rapidly equate their voltage before regeneration phase kicks start. In addition, the input capacitance of a NAND based latch following the regeneration stage is isolated from the regeneration nodes by inserting two inverters. An input-referred offset cancellation circuit, which adjusts the body voltages of the input triple-well NFET transistors, is designed. It consists of a 7-bit counter, a 7-bit resistive digital-to-analog converter (DAC), and a digital logic controller. The comparator is able to detect an input voltage as small as LSB/4 at 600-MHz clock frequency. In order to reduce the input loading capacitance of the split CDAC, an extra unit capacitor is added to the right-side array and the input is only sampled onto the bottom plates of the right-side array. Capacitance mismatch between the lowest-bit capacitor of the right-side array and the capacitors of the left-side array is digitally calibrated. The ADC is designed and fabricated in a 65-nm complementary metal oxide semiconductor (CMOS) process. Their static and dynamic performances are verified with on-PCB measurement. The ADC achieves an SNDR of 58.95 dB at 23.068-MHz input frequency and 50-MS/s sampling rate. Power consumption is 2.48 mW at 50-MS/ sampling rate. Its figure of merit (FOM) is 95 fJ/conversion-step. The ADC design presented in this thesis can be used either as a sub-ADC in time-interleaving ADCs or as a single-standing ADC for applications requiring a sampling rate up to 50 MS/s and a resolution of 11 bits.
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ItemA super low power MICS band receiver on 65 nm CMOS for high resolution retinal prosthesis( 2011)Implantable biomedical communication devices are now at the forefront of extensive research. These devices may effectively capture vital information from the outside environment for patients to use as substitutes of human organs (e.g. bionic ear, bionic eye, etc.), and/or record real-time physiological parameters from a patient (e.g. electrocardiogram, electroencephalogram, electromyogram, blood pressure, etc.). Transceivers for these purposes require extremely low power consumption, since batteries are undesirable due to their limited lifetime and the possibility of infections, and hence power is preferably acquired by wireless coupling. Moreover, these transceivers are usually preferred to be fully integrated on a single chip for easier surgery and better biocompability. Medical Implant Communication Service (MICS) band (402 MHz - 405 MHz with 10 channels), which was established by the Federal Communications Commission (FCC) of the United States in 1999, is widely used as the operation frequency band for biomedical devices. This thesis presents a super low power MICS band receiver for a fully integrated retinal prosthesis (Bionic Eye). In order to achieve super low total power consumption, all the analog blocks in this work are operated in subthreshold region and various low power techniques are applied. The fully subthreshold operation in MICS band is become possible due to the use of sub-70 nm Complementary Metal Oxide Semiconductor (CMOS) technology. This thesis starts with the power considerations in deep sub-micron CMOS and analyses the limits and challenges in low power radio frequency (RF) and analog design. It then considers subthreshold operation and provides parameter extraction approaches for the Enz-Krummenacher-Vittoz (EKV) model, as well as the modeling of transconductance efficiencies for various types of field-effect transistor (FET) devices. A literature review of MICS receivers is also included, in order to gain an intuitive insight into the current state of the art and the basic approaches that can be used for low power design. After presenting the system architecture and system level calculations, the individual block designs are reported one by one. The first block is the front-end down converter. This down converter, including a low-noise amplifier (LNA) and a quadrature mixer, only draws 500-μA bias current under 1-V supply. With a small differential local oscillation (LO) swing of 300 mV, it provides a voltage conversion gain of 34 dB and a noise figure of 7 dB, while a -27.5-dBm input-referred third-order intercept point (IIP3) is obtained. A power-constrained noise optimization technique is applied to this subthreshold down converter to optimize the matching parameters and transistor sizes. The second block is the channel selection filter. A 5th-order elliptic operational transconductance amplifier-capacitor (OTA-C) bandpass filter utilizes subthreshold inverter-based OTAs is designed. In order to broaden input range of the filter, the first OTA stage is linearized by using the active-error feedforward technique. The overall filter only draws 320-μA bias current under 1-V supply, while having an input range up to 0.6 Vpp and an in-band spurious free dynamic range (SFDR) of 41 dB. By using N-type FET capacitors as OTAs’ load, the chip area of this filter is minimized. Apart from the real bandpass filter, a 7th-order complex filter that has 48-dB image rejection at cost of 500-μW power dissipation is also constructed for the occasions that there exist image frequency interferences. As MICS band channel selection filters, both the real and complex filters have approximately 300-kHz bandwidths and exhibit more than 40-dB attenuations to the adjacent channel. The third block is the intermediate frequency (IF) variable gain amplifier (VGA). This VGA consists of a variable gain stage, followed by a fixed gain stage. It has a 32 dB log-linear tuning range and only requires 46-μA bias current under 1-V supply. The above three blocks constitute the receiver chain, which has a tunable total voltage gain of 36.8-68.9 dB on 50-Ω load and a noise figure of 17.2-15.1 dB. The measured gain and noise figure at designed normal operation condition, for a RF input power of -70 dBm, are 57.3 dB and 15.7 dB respectively. This thesis also reports on a subthreshold voltage-controlled oscillator (VCO) and a low power phase-locked loop (PLL), which are designed to provide LO signals for both receiver and transmitter in multi-channel operation. Current-reuse topology that uses N-type and P-type CMOS cross-coupled pairs is chosen for the core VCO design to save power. Cascade on-chip inductors are used and a pair of ”nCap” varactors (N-type FET in N-well) is configured to give a VCO gain of 12 MHz/V. The VCO is able to produce 600-mVpp quadrature signal whilst only dissipating 220 μW. The PLL utilizes digital frequency synthesizer and can settle within 350 μS while possessing a low phase noise, less than -102 dBc/Hz at 200-kHz offset. The average power dissipation of the entire PLL is a mere 400 μW. A 300-MHz microelectromechanical (MEMS) resonator is proposed to generate the system’s frequency reference. After comparing different types of MEMS devices and their post-CMOS micro-machining processes, a contour mode nickel disk resonator is selected. The precise modeling and simulations ensure it has a quality factor as high as 9000. The integration of the receiver chain with the PLL, including electrostatic discharge (ESD) protections, are demonstrated on a test chip using IBM 10cmoslpe 65-nm process. The performances of all individual blocks are measured and documented. Finally, experimental results of the entire receiver are reported and block power consumptions are experimentally established. The extremely low power dissipation and MICS band operation ensure that this receiver is very suitable for biomedical applications such as the Bionic Eye.