Enabling cutting-edge semiconductor simulation through grid technology
AuthorReid, Dave; Millar, Campbell; Roy, Scott; Roy, Gareth; SINNOTT, RICHARD; Stewart, Gordon; Stewart, Graeme; Asenov, Asen
Source TitleRoyal Society of London Philosophical Transactions A: Mathematical, Physical and Engineering Sciences
PublisherThe Royal Society
University of Melbourne Author/sSinnott, Richard
Document TypeJournal Article
CitationsReid, D., Millar, C., Roy, S., Roy, G., Sinnott, R., Stewart, G., et al. (2009 ). Enabling cutting-edge semiconductor simulation through grid technology. Royal Society of London Philosophical Transactions A: Mathematical, Physical and Engineering Sciences, 367(1897), 2573–2584.
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Publisher’s version is restricted access in accordance with The Royal Society policy. The original publication is available at http://rsta.royalsocietypublishing.org
The progressive scaling of Complementary Metal Oxide Semiconductor (CMOS) transistors drives the success of the global semiconductor industry. This is often described by the widely known Moore’s Law. As device dimensions approach the nanometer scale however, chip and systems designers must overcome many fundamental challenges. The EPSRC-funded project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) has been formed to explore and tackle the problems caused when working at the atomistic scale throughout the electronics design process. This paper outlines the recent scientific results of the project, and describes the way in which the scientific goals have been reflected in the grid-based e-infrastructure.
Keywordsnano complementary metal oxide semiconductor electronics; virtual organization; security; variability
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