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dc.contributor.authorReid, Daveen_US
dc.contributor.authorMillar, Campbellen_US
dc.contributor.authorRoy, Scotten_US
dc.contributor.authorRoy, Garethen_US
dc.contributor.authorSINNOTT, RICHARDen_US
dc.contributor.authorStewart, Gordonen_US
dc.contributor.authorStewart, Graemeen_US
dc.contributor.authorAsenov, Asenen_US
dc.date.accessioned2014-05-21T22:02:27Z
dc.date.available2014-05-21T22:02:27Z
dc.date.issued2009en_US
dc.identifier.citationReid, D., Millar, C., Roy, S., Roy, G., Sinnott, R., Stewart, G., et al. (2009 ). Enabling cutting-edge semiconductor simulation through grid technology. Royal Society of London Philosophical Transactions A: Mathematical, Physical and Engineering Sciences, 367(1897), 2573–2584.en_US
dc.identifier.urihttp://hdl.handle.net/11343/28773
dc.descriptionPublisher’s version is restricted access in accordance with The Royal Society policy. The original publication is available at http://rsta.royalsocietypublishing.orgen_US
dc.description.abstractThe progressive scaling of Complementary Metal Oxide Semiconductor (CMOS) transistors drives the success of the global semiconductor industry. This is often described by the widely known Moore’s Law. As device dimensions approach the nanometer scale however, chip and systems designers must overcome many fundamental challenges. The EPSRC-funded project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) has been formed to explore and tackle the problems caused when working at the atomistic scale throughout the electronics design process. This paper outlines the recent scientific results of the project, and describes the way in which the scientific goals have been reflected in the grid-based e-infrastructure.en_US
dc.languageengen_US
dc.publisherThe Royal Societyen_US
dc.relation.isversionofhttp://rsta.royalsocietypublishing.org.ezp.lib.unimelb.edu.au/content/367/1897/2573.full.pdf+htmlen_US
dc.subjectnano complementary metal oxide semiconductor electronicsen_US
dc.subjectvirtual organizationen_US
dc.subjectsecurityen_US
dc.subjectvariabilityen_US
dc.titleEnabling cutting-edge semiconductor simulation through grid technologyen_US
dc.typeJournal Articleen_US
melbourne.peerreviewPeer Revieweden_US
melbourne.affiliationThe University of Melbourneen_US
melbourne.publication.statusPublisheden_US
melbourne.source.titleRoyal Society of London Philosophical Transactions A: Mathematical, Physical and Engineering Sciencesen_US
melbourne.source.volume367en_US
melbourne.source.issue1897en_US
melbourne.source.pages2573–2584en_US
melbourne.elementsidNA
melbourne.contributor.authorSinnott, Richard
melbourne.accessrightsThis item is currently not available from this repository


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