Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid
AuthorWalker, JA; Sinnott, R; Stewart, G; Hilder, JA; Tyrrell, AM
Source TitlePHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES
University of Melbourne Author/sSinnott, Richard
Document TypeJournal Article
CitationsWalker, J. A., Sinnott, R., Stewart, G., Hilder, J. A. & Tyrrell, A. M. (2010). Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid. PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES, 368 (1925), pp.3967-3981. https://doi.org/10.1098/rsta.2010.0150.
Access StatusThis item is currently not available from this repository
C1 - Journal Articles Refereed
The project Meeting the Design Challenges of nano-CMOS Electronics (http://www.nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits.
KeywordsSoftware Engineering; Information Systems Management; Information Processing Services (incl. Data Entry and Capture)
- Click on "Export Reference in RIS Format" and choose "open with... Endnote".
- Click on "Export Reference in RIS Format". Login to Refworks, go to References => Import References