Interleaving techniques for high speed data transmission

Abstract

Interleaving is a technique used to convert a transmission channel with memory into one that is memoryless. The performance of Forward Error Correction (FEC) systems operating in the presence of burst errors is improved by passing the coded signal through an interleaving process. Commercial FEC sub-systems such as Viterbi and Reed-Solomon decoders are now commonplace, however interleavers, while indispensable, are still quite rare.

This dissertation provides a comprehensive review of the two main interleaver types: block and convolutional interleavers. Following this review, the optimum convolutional interleaver is chosen for further analysis. To gain some "real-time" experience and to investigate the commercial potential of a convolutional interleaver, a variable rate interleaver has been successfully implemented on a TMS320C51 Digital Signal Processor (DSP). Many factors were considered in this implementation: throughput, synchronisation, interleaving depth and full-duplex interleaving and de-interleaving. To test the implementation, the proposed convolutional interleaver was finally interfaced to a commercial 1024 QAM 2Mbit/s modem.

The investigation of the implementation of interleavers with DSP indicates that there is a need for more compact and flexible interleaver structures which can be readily integrated (in VLSI or DSP). The final part of the dissertation focused on cascaded and adaptive interleavers. Cascaded interleavers allow more sophisticated interleavers to be constructed from simple interleaving blocks. Adaptive interleavers provide the ability to adjust the interleaving depth (and thus the burst error protection) dynamically. A comprehensive computer simulation was developed and used for these investigations. The previously mentioned DSP based interleaver was also interfaced to the host personal computer (PC). This system facilitates rapid simulation results with the interleaving part of the simulation being run in real-time.

In summary, this thesis provides new designs and associated implementation results for various interleaving systems including high speed single chip, variable rate, byte oriented convolutional interleavers. Based on a novel dynamic interleaver concept, a new adaptive interleaving system is proposed and this is supported with successful simulation results for advanced high speed data transmission system.