TY  - JOUR
AU  - Reid, Dave
AU  - Millar, Campbell
AU  - Roy, Scott
AU  - Roy, Gareth
AU  - SINNOTT, RICHARD
AU  - Stewart, Gordon
AU  - Stewart, Graeme
AU  - Asenov, Asen
Y2  - 2014/05/21
Y1  - 2009
UR  - http://hdl.handle.net/11343/28773
AB  - The progressive scaling of Complementary Metal Oxide Semiconductor (CMOS) transistors drives the success of the global semiconductor industry. This is often described by the widely known Moore’s Law. As device dimensions approach the nanometer scale however, chip and systems designers must overcome many fundamental challenges. The EPSRC-funded project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) has been formed to explore and tackle the problems caused when working at the atomistic scale throughout the electronics design process. This paper outlines the recent scientific results of the project, and describes the way in which the scientific goals have been reflected in the grid-based e-infrastructure.
LA  - eng
PB  - The Royal Society
KW  - nano complementary metal oxide semiconductor electronics
KW  - virtual organization
KW  - security
KW  - variability
T1  - Enabling cutting-edge semiconductor simulation through grid technology
IS  - Royal Society of London Philosophical Transactions A: Mathematical, Physical and Engineering Sciences
VL  - 367
IS  - 1897
SP  - 2573–2584
L1  - /bitstream/handle/11343/28773/264018_Sinnott_enabling.pdf?sequence=1&isAllowed=n
ER  -